VHDL Training

• VHDL
  This 5 day hands on course presents the elements of the VHDL language (with an emphasis on synthesizable features). It concentrates on the language structures of VHDL.   The class is very lab intensive with a minimum of 50% of the time spent on lab exercises. These exercises are a combination of small exercises reinforcing the topics in the lecture, and longer exercises that allow the student to work on “real world” problems.
  
  Course Contents
  Day 1
  • VHDL Design Flow
  • Design Units – Entities, Architecture, Packages
  • Data Types & Math, Logic, Relational Operators
  • Vectors
  • Concurrent/Sequential Statements
  • Combinatorial & Clocked Processes
  • Hierarchy & Structural VHDL
  • Introduction to Testbenches
  
  Day2
  • Review of Fundamental VHDL Concepts
  • Vector Operations & Advanced Manipulation
  • Tri-States & Bi-directional Signals
  • VHDL Processes – Advanced Topics
  • Design Re-use – Generics
  • Device Specific Coding
  • IEEE Library
  • Testing Clocked Circuits
  
  Day 3
  • Synchronous Designs
  • Variables, Packages , & Subprograms
  • State Machines
  • Device Specific Coding
  • Post Synthesis Simulation
  • Synthesizing Don’t Cares
  
  Day 4
  • Advanced Data Types
  • RAM Structures
  • LFSR’s
  • Synthesis Factors
  • Incremental Synthesis
  • Subprogram Overloading & Recursions
  
  Day 5
  • Generate Statement
  • Behavioral Modeling
  • Modeling Delays
  • Simulator Concepts
  • Configurations
  • Design Packages & Libraries
  • File & Text I/O

• Verilog
  This 5 day hands on course presents the elements of the Verilog language (with an emphasis on synthesizable features). It concentrates on the language structures of Verilog (including the 2001 update).  The class is very lab intensive with a minimum of 50% of the time spent on lab exercises. These exercises are a combination of small exercises reinforcing the topics in the lecture, and longer exercises that allow the student to work on “real world” problems.
  
  Course Contents
  

  Day 1
  Basic Verilog Design Structure
  	Effective use of conditional constructs (if-else, case, casez, ?:) Synthesis Friendly Synchronous Constructs V2K1 @* and comma-separated sensitivity lists Hierarchy and Port Connection Rules Shifting & Concatenation
  Immediate Numbers and Math in Verilog
  	Verilog ‘95 Verilog 2K1
  Using Blocking vs Non Blocking Statements
  Intro to test structures
  Day2
  Verilog Array Structures
  Single dimension Multi dimension (V2K1) Part Selects Memory Structures
  Parameterizing Verilog Modules
  	Defparam Inline Re-parameterizations Local Parameters Parameters vs. `define
  Conditional Compilation for Design and Verification
  ‘include directive ‘ifdef `define
  Verilog Test Structures
  	Efficient testing Concepts (self checking) Monitoring Verilog ’95 File structures V2K1 enhanced File I/O Fork/Joins Verilog Procedural Assign Statement Verilog Simulator Structure and Avoiding Synthesis Mismatches
  Day 3
  Verilog Library structures
  	Importance of Post Synthesis and Timing Simulations
  Device Specific Coding
  Device Specific Macro Generators (Cores)
  Verilog Synthesis Techniques
  	Mixed Design Sources Incremental Synthesis
  Post Synthesis Simulations
  Subprograms with Verilog
  	Functions Tasks
  Advanced loops, tasks, and functions & V2K1 automatic tasks and functions
  State Machine Coding in Verilog
  	FSM Coding Styles for verilog single vs multiblock structures
  Day 4
  Verilog Configuration Files
  Arrays of Instance & V2K1 Generate Statements
  Behavioral Modeling
  Modeling Timing Delays
  Specify Blocks
  Dumpfiles and Waveform Viewer Strategies
  Timing Simulations in Verilog
  Verilog/VHDL Contrasts
  The PLI C Function Interface
  Day 5
  System Verilog 3.0 Introduction
  Advanced Data Types
  	Classes 2value vs. 4value logic Packed & Unpacked arrays Structures & Unions Enumerated Data Types
  System Verilog Classes
  	Definitions Inheritance
  Associative Arrays
  	Inserting values Extracting values
  Random Data Generation
  	Generating Random Numbers Random Constraints Rand Constraint generation Rand Constraint Generation based on permutations
  Assertions
  	Immediate Assertions Concurrent Assertions Simple Sequences

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For information on Xilinx Training courses in:

Canada, Quebec, New England regions:
Contact Chris Green the training coordinator for Hardent Xilinx Authorized Training Partner (ATP)

Northeast and Mid-Atlantic regions:
Contact Ed McCauley the sales representative for Bottom Line Technologies Inc., Xilinx Authorized Training Partner (ATP)

For any other regions contact Xilinx directly.
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